2024-07-14 - tech

Why are chiplets so important in the automotive field

In the future, small chips will become the focus of both the automotive and chip industries.

The degree of electrification in the automotive market is continuously increasing, and competition is becoming more intense, forcing companies to accelerate the design and production process.

Facing an extremely short market window and constantly changing demands, some of the largest and most well-known automobile manufacturers are striving to maintain competitiveness. Unlike the past where automobile manufacturers typically had a design cycle of five to seven years, the latest technologies on cars today are likely to be considered obsolete within a few years. If they cannot keep up, a host of new startups producing inexpensive cars will emerge, capable of updating or changing features as quickly as software updates.

However, software has limitations in terms of speed, safety, and reliability, and the ability to customize hardware is a direction many automobile manufacturers are currently working towards. This is where chips have an advantage, and the current focus is on how to establish sufficient interoperability within a large ecosystem to make it a plug-and-play market. Key factors for achieving automotive chip interoperability include standardization, interconnect technology, communication protocols, power and thermal management, security, testing, and ecosystem collaboration.

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Similar to non-automotive applications at the circuit board level, much of the design work focuses on chip-to-chip approaches, which has also driven many novel design considerations and trade-offs. At the chip level, due to the increased performance requirements, the interconnections between various processors, chips, memory, and I/O are becoming increasingly complex, leading to a multitude of standard requirements. Different interconnect and interface types have been proposed for different purposes, and emerging chip technologies for specialized functions (such as processors, memory, and I/O) are changing the methods of chip design.

Siemens EDA Vice President of Virtual and Mixed-Signal Systems, David Fritz, said: "Automotive original equipment manufacturers have realized that to control their own destiny, they must control their own SoC." Furthermore, they believe that adopting the latest process nodes is necessary, where the cost of a single mask set can reach up to 100 million USD. They cannot afford it. They also cannot secure the talent. In summary, the original equipment manufacturers realize that to master their own destiny, they need a technology that is developed by other companies but can be combined as needed to produce unique differentiated products that they believe will not become obsolete for at least a few years. Only then does it become economically feasible. The only thing that meets the requirements is the chip.

Chipsets can be optimized for specific functions, helping automobile manufacturers leverage technology that has been proven in a variety of car designs to meet reliability, safety, and security requirements. Additionally, they can shorten the time to market for products and ultimately reduce the cost of different features and functions.

Over the past decade, the demand for chips has been on an upward trend. According to a forecast by Allied Market Research, global automotive chip demand is expected to grow from $49.8 billion in 2021 to $121.3 billion by 2031. This growth will attract more automotive chip innovation and investment, and chips are expected to be a major beneficiary.However, the maturation of the small chip market will still take some time and may be rolled out in phases. Initially, suppliers will offer proprietary modules of different specifications. Then, partners will work together to provide small chips that support each other, as some suppliers have already done. The final stage will be universally interoperable small chips, supported by UCIe or other interconnect solutions.

Reaching the final stage will be the most challenging and will require significant changes. To ensure interoperability, a critical mass of the automotive ecosystem and supply chain must come together, including hardware and software developers, foundries, OSATs, and material and equipment suppliers.

Momentum is building

On the positive side, not all of this is starting from scratch. At the circuit board level, modules and subsystems have always used on-board chip-to-chip interfaces and will continue to do so in the future. Various chip and IP providers, including Cadence, Diode, Microchip, NXP, Renesas, Rambus, Infineon, Arm, and Synopsys, offer off-the-shelf interface chips or IP to create interface chips.

Arif Khan, Director of Advanced Product Marketing for Design IP at Cadence, said: "Driven by necessity, Chiplets have emerged. The ever-growing size of processors and SoCs is reaching the limits of lithography and economies of scale. The incremental benefits brought by process technology advancements are less than the rise in cost per transistor and design. Advances in packaging technology (2.5D/3D) and standardization of chip-to-chip interfaces (such as UCIe) will promote the development of small chips."

Almost all chips currently in use are developed in-house by large chip manufacturers like Intel, AMD, and Marvell, as they can tightly control the characteristics and behavior of these chips. However, efforts are being made at all levels to open up this market to more participants. At that time, smaller companies will be able to start leveraging the achievements of the high-profile pioneers to date and innovate around these developments.

Guillaume Boillet, Senior Director of Strategic Marketing at Arteris, said: "Many of us believe that the dream of having off-the-shelf, interoperable chip combinations will likely take years to become a reality. This also increases the appeal of FPGAs and eFPGAs, which can provide a certain degree of customization and updates for field hardware."

Geoff Tate, CEO of Flex Logix, said: "Chiplets are a real thing. Now, it is much more economical for a company to produce two or more chip sets than to produce near-micron-sized chips with almost no yield. Chip standardization still seems far away. Even UCIe is not yet a fixed standard. Not everyone agrees on issues such as UCIe, bare die testing, and who is responsible when integrated packaging does not work. We do have some customers who are using or evaluating eFPGA interfaces, and the standards for these interfaces (such as UCIe) are still evolving. They can implement chips now and later use eFPGAs to adapt to changes in standards."

There is also support from other aspects, such as the rising cost of device expansion and the need to integrate more functions into chips. However, these efforts also pave the way for automotive chips, and the industry also provides strong support for achieving all of this. For example, under the sponsorship of SEMI, ASME, and three IEEE societies, the new Heterogeneous Integration Roadmap (HIR) studies various microelectronics design, material, and packaging issues, setting a roadmap for the semiconductor industry. Their current focus includes 2.5D, 3D-IC, wafer-level packaging, integrated photonics, micro-electromechanical systems (MEMS) and sensors, as well as system-level packaging (SiP), aerospace, automotive, and more.At the recently held 2023 Heterogeneous Integration Global Summit, representatives from companies such as AMD, Applied Materials, ASE Technology, Lam Research, MediaTek, Micron, Onto Innovation, and TSMC expressed strong support for chip sets. Another organization that supports chips is the Chip Design Exchange (CDX) working group, which is part of the Open Domain-Specific Architecture (ODSA) and the Open Compute Project Foundation (OCP). The CDX charter focuses on various features of chips and chip integration, including electrical, mechanical, and thermal design exchange standards for 2.5D stacking and 3D Integrated Circuits (3D-IC). Its representatives include Ansys, Applied Materials, Arm, Ayar Labs, Broadcom, Cadence, Intel, Macom, Marvell, Microsemi, NXP, Siemens EDA, Synopsys, and others.

Siemens' Fritz noted, "Automotive companies are still in flux regarding the functional requirements for each chip." This is what we need. These companies can do such work, and then you can put them together. In this way, interoperability is not a big issue. Original equipment manufacturers might say, "I have to deal with all possibilities," making things overly complex. Another option is that they could say, "This is like high-speed PCIe. If I want to communicate from one interface to another, I already know how to do it. I already have the drivers running the operating system. This can solve a lot of problems, and I believe this is ultimately how it will be."

Standard interfaces enable SoC customization

It is not yet entirely clear how much overlap there will be between standard processors (which most chip sets currently use) and chip sets developed for automotive applications. However, as this technology enters new markets, its underlying technology and development will certainly promote each other.

David Ridgeway, Senior Product Manager of IP Acceleration Solutions at Synopsys, pointed out, "Whether it's AI accelerators or ADAS automotive applications, customers need standard interface IP blocks." It is crucial to provide comprehensively verified IP subsystems around customer IP customization requirements to support the subsystem components used in customer SoCs. When I say customization, you may not realize how high the degree of customization in IP has been at the physical layer and controller over the past 10 to 20 years. For example, PCI Express has evolved from PCIe Generation 3 to Generation 4, Generation 5, and now Generation 6. Controllers can be configured to support various split modes for smaller link widths, including one x16, two x8, or four x4. Our subsystem IP team works with customers to ensure that all customization requirements are met. For AI applications, signal and power integrity are extremely important to meet their performance requirements. Almost all of our customers are seeking breakthroughs to achieve the highest possible memory bandwidth speeds, allowing their TPUs to process more transactions per second. For any cloud computing or AI application, customers want the fastest response times.

The ultimate goal of optimizing PPA is to improve efficiency, which makes small chips particularly attractive in automotive applications. As UCIe matures, it is expected that overall performance will increase exponentially. For example, UCIe can provide a bandwidth of 28 to 224 GB/s/mm in standard packaging and 165 to 1317 GB/s/mm in advanced packaging. This means a 20 to 100 times improvement in performance. Reducing latency from 20 nanoseconds to 2 nanoseconds represents a 10-fold improvement. Another advantage is a 10-fold increase in power efficiency, at 0.5 pJ/b (standard packaging) and 0.25 pJ/b (advanced packaging). The key is to minimize the interface distance as much as possible.

ConclusionThe idea of standardizing chip-to-chip interfaces is quickly gaining popularity, but achieving this goal requires time, effort, and a great deal of cooperation between companies that rarely communicate with each other. Building a car requires an automobile manufacturer. However, using chips to manufacture a car requires the collective efforts of the entire ecosystem, including developers, foundries, OSATs, material and equipment suppliers.

Automotive original equipment manufacturers are experts in system assembly and finding innovative ways to reduce costs. But can they quickly and effectively establish and utilize an ecosystem of interoperable chips to shorten design cycles, increase customization, and adapt to a world where the most advanced technology may already be outdated by the time it is fully designed, tested, and provided to consumers?

The commercial Chiplet ecosystem may still be a decade away.

Semiconductor Engineering sat down with Frank Schirrmeister, Vice President of Solutions and Business Development at Arteris, and Paul Karazuba, Vice President of Marketing at Expedera; Stephen Slater, EDA Product Management/Integration Manager at Keysight Technologies; Kevin Rinebold, Senior Customer Technology Manager for Advanced Packaging Solutions at Siemens EDA; Mayank Bhatnagar, Director of Product Marketing for the Silicon Solutions Group at Cadence; and Mick Posner, Vice President of Product Management for High-Performance Computing IP Solutions at Synopsys, to discuss the challenges of establishing a commercial chiplet ecosystem. Here is an excerpt from that discussion.

SE: There is a lot of discussion and activity around Chiplets today. What is your view on the current state of the commercial Chiplet ecosystem?

Schirrmeister: There is a lot of interest in open chiplet ecosystems today, but we may still be far from true openness. Proprietary versions of chiplets are still very active and thriving. We see them in designs. Our suppliers are all supporting these goals to make it a reality, just like UCIe supporters, but it will take some time to achieve a fully open ecosystem. We might need at least three to five years to reach a PCI Express-like interchange environment.

Bhatnagar: The commercial chiplet ecosystem is still in a very early stage. Many companies are offering chiplets, designing them, and shipping products, but they are still single-supplier products, with the same company designing all the parts. I hope that with the advancement of the UCIe standard and more standardization, we will eventually be able to provide a market-like environment for chiplets.

Karazuba: Organizations like AMD are very familiar with the commercialization of homogeneous chiplets. But there are still many questions regarding the commercialization of heterogeneous chiplets (i.e., chiplets from multiple suppliers).

Slater: We've been in a lot of board discussions and attended industry events like TSMC OIP, and there are many exciting things happening. I see many small and medium-sized customers starting to consider their development plans for what their chiplets should be. I do believe that those who will be the most successful first will be those in a single-generation foundry ecosystem like TSMC. Today, if you're choosing IP, you can choose which IP to go with in many ways, look at what has been taped out before and its success to manage risk and cost when you put things together. In the future, we will see that now you have choices. Are you buying IP or buying a chiplet? It is crucial that they all come from the same wafer fab and are assembled in the same way. Technical considerations such as UCIe standard packaging and advanced packaging, as well as technical factors like high-speed simulation analysis toolkits, will become more important.Rinebold: I've been working in this field for about 30 years, so I can trace back to the earliest days of multi-chip modules and so on. When we talk about ecosystems, there are many examples today where we see HBM and logic combined at the interposer level. If you consider HBM as a small chip, then that's valid, and it's a completely different argument. Some people consider HBM to be in that category. The idea of true Lego bricks, the combination and matching of small chips, is still the desire of the mainstream market, but there are also some business obstacles that need to be addressed. Similarly, there are exceptions with some single-supplier solutions, which are more or less homogeneous integration, or a completely vertically integrated environment where a single supplier integrates their small chips into some very impressive packaging.

Posner: "Aspiration" is the word we use to describe an open ecosystem. I would say with a bit of frustration that I believe this is a 5 to 10-year thing. Is it possible? Absolutely. But the biggest problem we see right now is a huge knowledge gap about what it really means. As tech companies understand more about what this means, we will see an acceleration in adoption. But within what we call the "proprietary" realm—single companies or micro-ecosystems—we see multi-chip systems on the rise.

SE: Is it possible to define from a technical standpoint the various pieces we have today that would make a commercial chiplet ecosystem a reality?

Rinebold: It's encouraging to see the establishment of standards. We've mentioned some of the chip-to-chip protocols like UCIe. Organizations like JEDEC have announced extending their JEP30 PartModel format to the Chiplet ecosystem to incorporate chiplet-style data. Most of the work has been incorporated into the CDX working group under Open Compute. This is encouraging. There were some earlier comments about the open market. I agree that it might take us another 3 to 10 years to achieve this goal. The underlying framework and infrastructure are already in place, but many licensing and distribution issues must be addressed before we see any kind of widespread adoption.

Posner: The infrastructure is available. EDA tools for creating, packaging, analyzing, simulating, manufacturing—are all there. The intellectual property around it, whether it's UCIe or some more traditional chip-to-chip interfaces, is there. What hasn't been established is the complete methodology and process for achieving interoperability. Everything within the confines is possible, but the broader ecosystem, the market, will require chip interoperability, simulation, packaging, and so on. This is the area we think is missing but is still being built.

Schirrmeister: Do we know what we need? We might be able to define it quite well. If the vision is an open ecosystem with IP on chiplets that you can piece together like Lego bricks, then the IP industry would tell us what we need, and then there are some gaps above them. I hear people from the hard-coded IP world talking about something equivalent to a PDK for chiplets, but today's IP ecosystem and IP deliverables tell us that it doesn't work like Lego bricks yet. We're making progress every year. When you break it down into chiplets and protocols, we need to think hard about what the additional challenges are. Then, you have to deal with significant systemic issues, such as how to handle consistency between chiplets? Doing it on a chip is challenging enough. Now, you might have to deal with other partners that you don't even own. This is not a confined environment within an open ecosystem. It makes it very challenging, and it creates job security for at least 5 to 10 years.

Bhatnagar: On the technical side, what's going well is adoption. We can see big companies like Intel, and of course, IP providers like us and Synopsys. Everyone is working towards standardizing chiplet integration, and it's going very well. EDA tools are also coming out to support this. But we are far from the market because there are still many issues unresolved, such as licensing and other things that will take more time.

Slater: The standard bodies and networking groups have excited a lot of people, and we've had a lot of customers coming in. I'm wondering if this is only applicable to very high-end computing? From the companies I see in these forums, even automotive or aerospace/defense companies are planning for the next 10 years or more. Take automotive, for example; this company is considering creating chiplets for internal consumption, so they might reorganize how they view the creation of many different variants or evolutions of their products, trying to implement them as more modular types of chiplet blocks. "If we take the microprocessor as part of it, would we sell it as a chiplet to other customers to integrate into larger designs?" For me, the epiphany moment was seeing how broad the application range is.

I do think the standard work is progressing very quickly and is going very well. For example, at Keysight EDA, we just released a chiplet PHY designer. It's a simulation of the UCIe high-speed digital link, which can only be achieved by releasing standards, so EDA companies can look at it and understand what they need to do with it. EDA tools are ready to handle such things. Perhaps the last point is that for sharing IP, to ensure its availability, database and process management will become more important. You need to track which chip was manufactured in which process and be able to provide it within the company to other potential users of that chip.

SE: From a business perspective, what progress has been made so far, and what still needs to be addressed?Karazuba: From a business perspective, strictly speaking, heterogeneous chiplets, I don't think anything is really in place. Let me define this by asking "Who is responsible for the warranty?" Who is responsible for testing? Who is at fault? Who is responsible for the supply chain? For homogeneous chiplets or monolithic silicon, this is understandable because that's how the industry has been conducting business since its inception. However, when you talk about chiplets from multiple vendors, with multiple IPs (and possibly different interfaces), manufactured at multiple fabs, then assembled by a third party, tested by a fourth party, and then shipped, what happens when something goes wrong? Who do you point the finger at? Who do you go talk to? If a specific chiplet is not operating as expected, it may not necessarily be the chiplet that's at fault. It could be another chiplet or the interface on the hub, whatever it is. We are on the verge of achieving this, but it's not clear who will be responsible for such things. Is it the multi-chip module manufacturer or the purchaser? I worry about going back to the Wintel problem, where the chipmaker points to the OS maker, the OS maker points to the hardware maker, and the OS maker points to the chipmaker. The understanding of the business aspect is the real obstacle to the adoption of chiplets. Indeed, the technology is much more difficult than the business, but I have no doubt that engineers will achieve this goal faster than business people.

Bhatnagar: From a business standpoint, what really matters is standardization. The internals of a chiplet are fine, but how it affects the other chiplets around it is important. We want to be able to make something and sell many copies of it. But without standardization, we are either gambling, pursuing only one thing and assuming everyone will switch to it, or we are making multiple versions of the same thing, which adds extra costs. To truly justify the business case for any chiplet or any type of chiplet IP, standardization is crucial for the electrical interconnects of the system, packaging, and all other aspects.It seems like you've included some non-text elements in your request. Please provide the text you would like me to translate into English, and I'll be happy to assist you.